Block Diagram Phase Locked Loop – PLL

Block Diagram Phase Locked Loop – PLL. A system that allows a certain signal to control the signal phase of an oscillator which is locked in a circle. The phase frequency oscillator can be as large or multiples of the frequency of the signal (hereinafter referred to as frequency-reference). If the frequency of the signal derived from a crystal oscillator frequency so that others can have the same stability defined by the frequency of the crystal. This became the basis of the Frequency Synthesizer.

If the reference frequency has a value varying the frequency of “ring oscillator” will follow the change. This principle is used in the demodulator FM (Frequency Modulation), FSK (Frequency Shift Keying) and Tracking Filter.

Here’s an example block diagram of Phase Locked Loop – PLL Classic Applicative working on FM-II 100-MHz :

Above principles better known as PLL (Phase Locked Loop) and has been known since 1923 but little used until the end of 1960. The parts of the PLL consists of :

  1. Fixed-frequency oscillator as a reference which is usually constructed using quartz crystals to ensure stability
  2. VCO (Voltage Control Oscillator) is an oscillator whose output frequency of the voltage controlled
  3. LPF (Low Pass Filter). This section basically changing so fast voltage swing of Phase Detector into dc voltage controlled phase
  4. LPF-Amplifier. This section reinforces the LPF output is still very weak up to the level of a few volts dc to be able to control the VCO
  5. n-Devider or “divisor n times”. The section that divides the desired output frequency of the VCO frequency equal to the so-reference
  6. Phase Detector. This part works by comparing the value of the reference frequency to the frequency of the n-Devider. Will output 0 volts if the same happens both frequency and dc value certain extent if the two frequencies are not the same

In terms of the function of each part of the above can be illustrated that the frequencies are in the “ring” is extremely stable reference frequency to match the stability of the crystal oscillator. The most decisive of the quality of a PLL is Respone Time of LPF and Devider and width of the field work at the level of the VCO control voltage. Design of the LPF value builder component is crucial to the PLL output (VCO) directly. Inaccuracy would cause Locking Time lasts a long time and this is an indication of the performance of the PLL is not good. Besides, can also cause side-tone is quite disturbing because it will be carried along in the implementation of FM modulation wave.

Block Diagram of Phase Locked Loop devider usually begins with a pre-scaller since most n-devider not able to work on the band-II. Thus there will be a number of stages before reaching the devider Phase Detector and this can be overcome by the use of TTL IC because his speed is unquestioned. On certain types of PLL determining the desired output frequency is used in two ways, namely through n-devider and changes in the reference frequency. Changes in the reference frequency can not be freely given Q n-devider very high-factory of crystal quartz that only allows shifting as wide as 2% of the fundamental frequency. This method is generally applicable to ordinary and AM-SSB Transceiver with Variable installing capacitor in series with the crystal to do the Fine-Tuning.

Use of quartz crystal as an oscillator has long since worn Q-factory of more than 3000 and its stability is awesome. As an illustration, if used clock / watch is the source of the beats made it to late quartz crystal or faster 1 second it takes 300 years.

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